verilog求助

下面这个最多延迟32拍，dly_num配置延迟数，如果din异步的，延迟一拍的(dly_num==0)不能用:
module delay(
input logic clk,
input logic rst_n,
input logic din,
input [4:0] dly_num,
output logic din_out
);
logic [31:0] din_dly;
assign din_out = din_dly[dly_num];
always@璐村惂鐢ㄦ埛_05NC135馃惥 posedge clk or negedge rst_n )
if( ~rst_n ) din_dly <= 32'b0;
else if din_dly <= {din_dly[31:1], din};
endmodule