大佬们！跪求如何解决这些问题！有重赏可以吧！解决了问题可以找

跪着求大佬们回答一下

Dddds

Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
Violation between Pad D9-2(142.748mm,120.546mm) Multi-Layer and
Track (35.56mm,121.92mm)(162.56mm,121.92mm) Top Layer
Violation between Pad D6-2(149.86mm,121.054mm) Multi-Layer and
Track (35.56mm,121.92mm)(162.56mm,121.92mm) Top Layer
Violation between Pad D12-2(157.988mm,122.07mm) Multi-Layer and
Track (35.56mm,121.92mm)(162.56mm,121.92mm) Top Layer
Violation between Pad D1-1(158.496mm,88.75mm) Multi-Layer and
Pad D3-2(157.48mm,86.51mm) Multi-Layer
Violation between Pad D7-1(149.352mm,86.21mm) Multi-Layer and
Pad D4-2(149.86mm,83.97mm) Multi-Layer
Rule Violations :5
Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Violation between Pad D6-2(149.86mm,121.054mm) Multi-Layer and
Tr

跪求大神！！！

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