代码如下
library ieee;
use ieee.std_logic_1164.all;
entity decoder416 is
port(
b_in :in std_logic_vector(3 downto 0);
d_out :out std_logic_vector(15 downto 0);
en :in std_logic;
);
end decoder416;
architecture behave of decoder416
begin
process(b_in)
begin
if en='1' then
case b_in is
when "0000"=>d_out<="1111111111111110";--0
when "0001"=>d_out<="1111111111111101";--1
when "0010"=>d_out<="1111111111111011";--2
when "0011"=>d_out<="1111111111110111";--3
when "0100"=>d_out<="1111111111101111";--4
when "0101"=>d_out<="1111111111011111";--5
when "0110"=>d_out<="1111111110111111";--6
when "0111"=>d_out<="1111111101111111";--7
when "1000"=>d_out<="1111111011111111";--8
when "1001"=>d_out<="1111110111111111";--9
when "1010"=>d_out<="1111101111111111";--10
when "1011"=>d_out<="1111011111111111";--11
when "1100"=>d_out<="1110111111111111";--12
when "1101"=>d_out<="1101111111111111";--13
when "1110"=>d_out<="1011111111111111";--14
when "1111"=>d_out<="0111111111111111";--15
when others=>d_out<="XXXXXXXXXXXXXXXX";--null
end case;
else
y<="1111111111111111";
end if;
end process;
end behave;
格式如图

编译提示
Error (10500): VHDL syntax error at /11.vhd(8) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"
那一句在这里

我是新手 只解决语法错误 ，，其他的先不管 谢谢