Linux version 2.6.18-164.el5 (mockbuild@builder10.centos.org) (gcc version 4.1.2 20080704 (Red Hat 4.1.2-46)) #1 SMP Thu Sep 3 03:28:30 EDT 2009
Command line: ro root=/dev/VolGroup00/LogVol00
BIOS-provided physical RAM map:
BIOS-e820: 0000000000010000 - 0000000000097c00 (usable)
BIOS-e820: 0000000000097c00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000008c3d1000 (usable)
BIOS-e820: 000000008c3d1000 - 000000008c4a5000 (ACPI NVS)
BIOS-e820: 000000008c4a5000 - 000000008c5a4000 (ACPI data)
BIOS-e820: 000000008c5a4000 - 000000008d9a4000 (ACPI NVS)
BIOS-e820: 000000008d9a4000 - 000000008f602000 (ACPI data)
BIOS-e820: 000000008f602000 - 000000008f64f000 (reserved)
BIOS-e820: 000000008f64f000 - 000000008f6e7000 (ACPI data)
BIOS-e820: 000000008f6e7000 - 000000008f6f0000 (ACPI NVS)
BIOS-e820: 000000008f6f0000 - 000000008f6f2000 (ACPI data)
BIOS-e820: 000000008f6f2000 - 000000008f7cf000 (ACPI NVS)
BIOS-e820: 000000008f7cf000 - 000000008f800000 (ACPI data)
BIOS-e820: 000000008f800000 - 0000000090000000 (reserved)
BIOS-e820: 00000000a0000000 - 00000000b0000000 (reserved)
BIOS-e820: 00000000fc000000 - 00000000fd000000 (reserved)
BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved)
BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000470000000 (usable)
DMI 2.5 present.
ACPI: RSDP (v002 INTEL ) @ 0x00000000000f0410
ACPI: XSDT (v001 INTEL S5500BC 0x00000000 0x01000013) @ 0x000000008f7fd120
ACPI: FADT (v004 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7fb000
ACPI: MADT (v002 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7f3000
ACPI: MCFG (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f2000
ACPI: HPET (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f1000
ACPI: SLIT (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f0000
ACPI: SRAT (v002 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7ef000
ACPI: SPCR (v001 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7ee000
ACPI: WDDT (v001 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7ed000
ACPI: SSDT (v002 INTEL SSDT PM 0x00004000 INTL 0x20061109) @ 0x000000008f7d2000
ACPI: SSDT (v002 INTEL IPMI 0x00004000 INTL 0x20061109) @ 0x000000008f7d1000
ACPI: HEST (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f7d0000
ACPI: BERT (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f7cf000
ACPI: ERST (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f6f1000
ACPI: EINJ (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f6f0000
ACPI: DSDT (v002 INTEL S5500BC 0x00000003 MSFT 0x0100000d) @ 0x0000000000000000
SRAT: PXM 0 -> APIC 0 -> Node 0
SRAT: PXM 1 -> APIC 32 -> Node 1
SRAT: PXM 0 -> APIC 2 -> Node 0
SRAT: PXM 1 -> APIC 34 -> Node 1
SRAT: PXM 0 -> APIC 18 -> Node 0
SRAT: PXM 1 -> APIC 50 -> Node 1
SRAT: PXM 0 -> APIC 20 -> Node 0
SRAT: PXM 1 -> APIC 52 -> Node 1
SRAT: PXM 0 -> APIC 1 -> Node 0
SRAT: PXM 1 -> APIC 33 -> Node 1
SRAT: PXM 0 -> APIC 3 -> Node 0
SRAT: PXM 1 -> APIC 35 -> Node 1
SRAT: PXM 0 -> APIC 19 -> Node 0
SRAT: PXM 1 -> APIC 51 -> Node 1
SRAT: PXM 0 -> APIC 21 -> Node 0
SRAT: PXM 1 -> APIC 53 -> Node 1
SRAT: Node 0 PXM 0 0-90000000
SRAT: Node 0 PXM 0 0-270000000
SRAT: Node 1 PXM 1 270000000-470000000
NUMA: Using 28 for the hash shift.
Bootmem setup node 0 0000000000000000-0000000270000000
Bootmem setup node 1 0000000270000000-0000000470000000
Memory for crash kernel (0x0 to 0x0) notwithin permissible range
disabling kdump
On node 0 totalpages: 2045374
DMA zone: 2613 pages, LIFO batch:0
DMA32 zone: 556041 pages, LIFO batch:31
Normal zone: 1486720 pages, LIFO batch:31
On node 1 totalpages: 2068480
Normal zone: 2068480 pages, LIFO batch:31
ACPI: PM-Timer IO Port: 0x408
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x20] enabled)
Processor #32 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
Processor #2 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x22] enabled)
Processor #34 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x12] enabled)
Processor #18 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x32] enabled)
Processor #50 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x14] enabled)
Processor #20 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x34] enabled)
Processor #52 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x21] enabled)
Processor #33 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x03] enabled)
Processor #3 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x23] enabled)
Processor #35 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x13] enabled)
Processor #19 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x33] enabled)
Processor #51 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x15] enabled)
Processor #21 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x35] enabled)
Processor #53 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x10] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x11] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x12] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x13] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x14] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x15] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x16] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x17] lapic_id[0xff] disabled)
ACPI: LAPIC_NMI (acpi_id[0x00] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x10] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x11] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x12] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x13] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x14] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x15] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x16] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x17] high level lint[0x1])
ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23
ACPI: IOAPIC (id[0x09] address[0xfec90000] gsi_base[24])
IOAPIC[1]: apic_id 9, version 32, address 0xfec90000, GSI 24-47
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
ACPI: IRQ0 used by override.
ACPI: IRQ2 used by override.
ACPI: IRQ9 used by override.
Setting APIC routing to clustered
ACPI: HPET id: 0x8086a401 base: 0xfed00000
Using ACPI (MADT) for SMP configuration information
Nosave address range: 0000000000097000 - 0000000000098000
Nosave address range: 0000000000098000 - 00000000000a0000
Nosave address range: 00000000000a0000 - 00000000000e0000
Nosave address range: 00000000000e0000 - 0000000000100000
Nosave address range: 000000008c3d1000 - 000000008c4a5000
Nosave address range: 000000008c4a5000 - 000000008c5a4000
Nosave address range: 000000008c5a4000 - 000000008d9a4000
Nosave address range: 000000008d9a4000 - 000000008f602000
Nosave address range: 000000008f602000 - 000000008f64f000
Nosave address range: 000000008f64f000 - 000000008f6e7000
Nosave address range: 000000008f6e7000 - 000000008f6f0000
Nosave address range: 000000008f6f0000 - 000000008f6f2000
Nosave address range: 000000008f6f2000 - 000000008f7cf000
Nosave address range: 000000008f7cf000 - 000000008f800000
Nosave address range: 000000008f800000 - 0000000090000000
Nosave address range: 0000000090000000 - 00000000a0000000
Nosave address range: 00000000a0000000 - 00000000b0000000
Nosave address range: 00000000b0000000 - 00000000fc000000
Nosave address range: 00000000fc000000 - 00000000fd000000
Nosave address range: 00000000fd000000 - 00000000fed1c000
Nosave address range: 00000000fed1c000 - 00000000fed20000
Nosave address range: 00000000fed20000 - 00000000ff800000
Nosave address range: 00000000ff800000 - 0000000100000000
Allocating PCI resources starting at b8000000 (gap: b0000000:4c000000)
SMP: Allowing 24 CPUs, 8 hotplug CPUs
Built 2 zonelists. Total pages: 4113854
Kernel command line: ro root=/dev/VolGroup00/LogVol00
Initializing CPU#0
PID hash table entries: 4096 (order: 12, 32768 bytes)
Console: colour VGA+ 80x25
Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
Checking aperture...
ACPI: DMAR not present
PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
Placing software IO TLB between 0x287f000 - 0x687f000
Memory: 16360104k/18612224k available (2547k kernel code, 355000k reserved, 1289k data, 208k init)
Calibrating delay loop (skipped), value calculated using timer frequency.. 4800.07 BogoMIPS (lpj=2400037)
Security Framework v1.0.0 initialized
SELinux: Initializing.
SELinux: Starting in permissive mode
selinux_register_security: Registering secondary module capability
Capability LSM initialized as secondary
Mount-cache hash table entries: 256
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 0/0 -> Node 0
using mwait in idle threads.
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
CPU0: Thermal monitoring enabled (TM1)
SMP alternatives: switching to UP code
ACPI: Core revision 20060707
Using local APIC timer interrupts.
result 8333551
Detected 8.333 MHz APIC timer.
SMP alternatives: switching to SMP code
Booting processor 1/16 APIC 0x20
Initializing CPU#1
Calibrating delay using timer specific routine.. 4799.98 BogoMIPS (lpj=2399994)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 1/20 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 0
CPU1: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 1: Syncing TSC to CPU 0.
CPU 1: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 2/16 APIC 0x2
Initializing CPU#2
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 2/2 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
CPU2: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 2: Syncing TSC to CPU 0.
CPU 2: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 3/16 APIC 0x22
Initializing CPU#3
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 3/22 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 1
CPU3: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 3: Syncing TSC to CPU 0.
CPU 3: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 4/16 APIC 0x12
Initializing CPU#4
Calibrating delay using timer specific routine.. 4800.02 BogoMIPS (lpj=2400012)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 4/12 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 9
CPU4: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 4: Syncing TSC to CPU 0.
CPU 4: synchronized TSC with CPU 0 (last diff -2 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 5/16 APIC 0x32
Initializing CPU#5
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399973)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 5/32 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 9
CPU5: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 5: Syncing TSC to CPU 0.
CPU 5: synchronized TSC with CPU 0 (last diff -6 cycles, maxerr 948 cycles)
SMP alternatives: switching to SMP code
Booting processor 6/16 APIC 0x14
Initializing CPU#6
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 6/14 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 10
CPU6: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 6: Syncing TSC to CPU 0.
CPU 6: synchronized TSC with CPU 0 (last diff -4 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 7/16 APIC 0x34
Initializing CPU#7
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 7/34 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 10
CPU7: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 7: Syncing TSC to CPU 0.
CPU 7: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 8/16 APIC 0x1
Initializing CPU#8
Calibrating delay using timer specific routine.. 4800.02 BogoMIPS (lpj=2400010)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 8/1 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
CPU8: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 8: Syncing TSC to CPU 0.
CPU 8: synchronized TSC with CPU 0 (last diff -2 cycles, maxerr 120 cycles)
SMP alternatives: switching to SMP code
Booting processor 9/16 APIC 0x21
Initializing CPU#9
Calibrating delay using timer specific routine.. 4799.93 BogoMIPS (lpj=2399968)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 9/21 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 0
CPU9: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 9: Syncing TSC to CPU 0.
CPU 9: synchronized TSC with CPU 0 (last diff -8 cycles, maxerr 960 cycles)
SMP alternatives: switching to SMP code
Booting processor 10/16 APIC 0x3
Initializing CPU#10
Calibrating delay using timer specific routine.. 4799.95 BogoMIPS (lpj=2399975)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 10/3 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
CPU10: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 10: Syncing TSC to CPU 0.
CPU 10: synchronized TSC with CPU 0 (last diff 2 cycles, maxerr 476 cycles)
SMP alternatives: switching to SMP code
Booting processor 11/16 APIC 0x23
Initializing CPU#11
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 11/23 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 1
CPU11: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 11: Syncing TSC to CPU 0.
CPU 11: synchronized TSC with CPU 0 (last diff -6 cycles, maxerr 940 cycles)
SMP alternatives: switching to SMP code
Booting processor 12/16 APIC 0x13
Initializing CPU#12
Calibrating delay using timer specific routine.. 4799.93 BogoMIPS (lpj=2399968)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 12/13 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 9
CPU12: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 12: Syncing TSC to CPU 0.
CPU 12: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 13/16 APIC 0x33
Initializing CPU#13
Command line: ro root=/dev/VolGroup00/LogVol00
BIOS-provided physical RAM map:
BIOS-e820: 0000000000010000 - 0000000000097c00 (usable)
BIOS-e820: 0000000000097c00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000008c3d1000 (usable)
BIOS-e820: 000000008c3d1000 - 000000008c4a5000 (ACPI NVS)
BIOS-e820: 000000008c4a5000 - 000000008c5a4000 (ACPI data)
BIOS-e820: 000000008c5a4000 - 000000008d9a4000 (ACPI NVS)
BIOS-e820: 000000008d9a4000 - 000000008f602000 (ACPI data)
BIOS-e820: 000000008f602000 - 000000008f64f000 (reserved)
BIOS-e820: 000000008f64f000 - 000000008f6e7000 (ACPI data)
BIOS-e820: 000000008f6e7000 - 000000008f6f0000 (ACPI NVS)
BIOS-e820: 000000008f6f0000 - 000000008f6f2000 (ACPI data)
BIOS-e820: 000000008f6f2000 - 000000008f7cf000 (ACPI NVS)
BIOS-e820: 000000008f7cf000 - 000000008f800000 (ACPI data)
BIOS-e820: 000000008f800000 - 0000000090000000 (reserved)
BIOS-e820: 00000000a0000000 - 00000000b0000000 (reserved)
BIOS-e820: 00000000fc000000 - 00000000fd000000 (reserved)
BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved)
BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000470000000 (usable)
DMI 2.5 present.
ACPI: RSDP (v002 INTEL ) @ 0x00000000000f0410
ACPI: XSDT (v001 INTEL S5500BC 0x00000000 0x01000013) @ 0x000000008f7fd120
ACPI: FADT (v004 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7fb000
ACPI: MADT (v002 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7f3000
ACPI: MCFG (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f2000
ACPI: HPET (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f1000
ACPI: SLIT (v001 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7f0000
ACPI: SRAT (v002 INTEL S5500BC 0x00000001 MSFT 0x0100000d) @ 0x000000008f7ef000
ACPI: SPCR (v001 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7ee000
ACPI: WDDT (v001 INTEL S5500BC 0x00000000 MSFT 0x0100000d) @ 0x000000008f7ed000
ACPI: SSDT (v002 INTEL SSDT PM 0x00004000 INTL 0x20061109) @ 0x000000008f7d2000
ACPI: SSDT (v002 INTEL IPMI 0x00004000 INTL 0x20061109) @ 0x000000008f7d1000
ACPI: HEST (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f7d0000
ACPI: BERT (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f7cf000
ACPI: ERST (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f6f1000
ACPI: EINJ (v001 INTEL S5500BC 0x00000001 INTL 0x00000001) @ 0x000000008f6f0000
ACPI: DSDT (v002 INTEL S5500BC 0x00000003 MSFT 0x0100000d) @ 0x0000000000000000
SRAT: PXM 0 -> APIC 0 -> Node 0
SRAT: PXM 1 -> APIC 32 -> Node 1
SRAT: PXM 0 -> APIC 2 -> Node 0
SRAT: PXM 1 -> APIC 34 -> Node 1
SRAT: PXM 0 -> APIC 18 -> Node 0
SRAT: PXM 1 -> APIC 50 -> Node 1
SRAT: PXM 0 -> APIC 20 -> Node 0
SRAT: PXM 1 -> APIC 52 -> Node 1
SRAT: PXM 0 -> APIC 1 -> Node 0
SRAT: PXM 1 -> APIC 33 -> Node 1
SRAT: PXM 0 -> APIC 3 -> Node 0
SRAT: PXM 1 -> APIC 35 -> Node 1
SRAT: PXM 0 -> APIC 19 -> Node 0
SRAT: PXM 1 -> APIC 51 -> Node 1
SRAT: PXM 0 -> APIC 21 -> Node 0
SRAT: PXM 1 -> APIC 53 -> Node 1
SRAT: Node 0 PXM 0 0-90000000
SRAT: Node 0 PXM 0 0-270000000
SRAT: Node 1 PXM 1 270000000-470000000
NUMA: Using 28 for the hash shift.
Bootmem setup node 0 0000000000000000-0000000270000000
Bootmem setup node 1 0000000270000000-0000000470000000
Memory for crash kernel (0x0 to 0x0) notwithin permissible range
disabling kdump
On node 0 totalpages: 2045374
DMA zone: 2613 pages, LIFO batch:0
DMA32 zone: 556041 pages, LIFO batch:31
Normal zone: 1486720 pages, LIFO batch:31
On node 1 totalpages: 2068480
Normal zone: 2068480 pages, LIFO batch:31
ACPI: PM-Timer IO Port: 0x408
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x20] enabled)
Processor #32 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
Processor #2 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x22] enabled)
Processor #34 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x12] enabled)
Processor #18 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x32] enabled)
Processor #50 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x14] enabled)
Processor #20 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x34] enabled)
Processor #52 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x21] enabled)
Processor #33 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x03] enabled)
Processor #3 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x23] enabled)
Processor #35 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x13] enabled)
Processor #19 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x33] enabled)
Processor #51 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x15] enabled)
Processor #21 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x35] enabled)
Processor #53 6:12 APIC version 21
ACPI: LAPIC (acpi_id[0x10] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x11] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x12] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x13] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x14] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x15] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x16] lapic_id[0xff] disabled)
ACPI: LAPIC (acpi_id[0x17] lapic_id[0xff] disabled)
ACPI: LAPIC_NMI (acpi_id[0x00] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x10] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x11] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x12] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x13] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x14] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x15] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x16] high level lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x17] high level lint[0x1])
ACPI: IOAPIC (id[0x08] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23
ACPI: IOAPIC (id[0x09] address[0xfec90000] gsi_base[24])
IOAPIC[1]: apic_id 9, version 32, address 0xfec90000, GSI 24-47
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
ACPI: IRQ0 used by override.
ACPI: IRQ2 used by override.
ACPI: IRQ9 used by override.
Setting APIC routing to clustered
ACPI: HPET id: 0x8086a401 base: 0xfed00000
Using ACPI (MADT) for SMP configuration information
Nosave address range: 0000000000097000 - 0000000000098000
Nosave address range: 0000000000098000 - 00000000000a0000
Nosave address range: 00000000000a0000 - 00000000000e0000
Nosave address range: 00000000000e0000 - 0000000000100000
Nosave address range: 000000008c3d1000 - 000000008c4a5000
Nosave address range: 000000008c4a5000 - 000000008c5a4000
Nosave address range: 000000008c5a4000 - 000000008d9a4000
Nosave address range: 000000008d9a4000 - 000000008f602000
Nosave address range: 000000008f602000 - 000000008f64f000
Nosave address range: 000000008f64f000 - 000000008f6e7000
Nosave address range: 000000008f6e7000 - 000000008f6f0000
Nosave address range: 000000008f6f0000 - 000000008f6f2000
Nosave address range: 000000008f6f2000 - 000000008f7cf000
Nosave address range: 000000008f7cf000 - 000000008f800000
Nosave address range: 000000008f800000 - 0000000090000000
Nosave address range: 0000000090000000 - 00000000a0000000
Nosave address range: 00000000a0000000 - 00000000b0000000
Nosave address range: 00000000b0000000 - 00000000fc000000
Nosave address range: 00000000fc000000 - 00000000fd000000
Nosave address range: 00000000fd000000 - 00000000fed1c000
Nosave address range: 00000000fed1c000 - 00000000fed20000
Nosave address range: 00000000fed20000 - 00000000ff800000
Nosave address range: 00000000ff800000 - 0000000100000000
Allocating PCI resources starting at b8000000 (gap: b0000000:4c000000)
SMP: Allowing 24 CPUs, 8 hotplug CPUs
Built 2 zonelists. Total pages: 4113854
Kernel command line: ro root=/dev/VolGroup00/LogVol00
Initializing CPU#0
PID hash table entries: 4096 (order: 12, 32768 bytes)
Console: colour VGA+ 80x25
Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
Checking aperture...
ACPI: DMAR not present
PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
Placing software IO TLB between 0x287f000 - 0x687f000
Memory: 16360104k/18612224k available (2547k kernel code, 355000k reserved, 1289k data, 208k init)
Calibrating delay loop (skipped), value calculated using timer frequency.. 4800.07 BogoMIPS (lpj=2400037)
Security Framework v1.0.0 initialized
SELinux: Initializing.
SELinux: Starting in permissive mode
selinux_register_security: Registering secondary module capability
Capability LSM initialized as secondary
Mount-cache hash table entries: 256
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 0/0 -> Node 0
using mwait in idle threads.
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
CPU0: Thermal monitoring enabled (TM1)
SMP alternatives: switching to UP code
ACPI: Core revision 20060707
Using local APIC timer interrupts.
result 8333551
Detected 8.333 MHz APIC timer.
SMP alternatives: switching to SMP code
Booting processor 1/16 APIC 0x20
Initializing CPU#1
Calibrating delay using timer specific routine.. 4799.98 BogoMIPS (lpj=2399994)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 1/20 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 0
CPU1: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 1: Syncing TSC to CPU 0.
CPU 1: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 2/16 APIC 0x2
Initializing CPU#2
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 2/2 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
CPU2: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 2: Syncing TSC to CPU 0.
CPU 2: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 3/16 APIC 0x22
Initializing CPU#3
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 3/22 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 1
CPU3: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 3: Syncing TSC to CPU 0.
CPU 3: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 4/16 APIC 0x12
Initializing CPU#4
Calibrating delay using timer specific routine.. 4800.02 BogoMIPS (lpj=2400012)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 4/12 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 9
CPU4: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 4: Syncing TSC to CPU 0.
CPU 4: synchronized TSC with CPU 0 (last diff -2 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 5/16 APIC 0x32
Initializing CPU#5
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399973)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 5/32 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 9
CPU5: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 5: Syncing TSC to CPU 0.
CPU 5: synchronized TSC with CPU 0 (last diff -6 cycles, maxerr 948 cycles)
SMP alternatives: switching to SMP code
Booting processor 6/16 APIC 0x14
Initializing CPU#6
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 6/14 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 10
CPU6: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 6: Syncing TSC to CPU 0.
CPU 6: synchronized TSC with CPU 0 (last diff -4 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 7/16 APIC 0x34
Initializing CPU#7
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 7/34 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 10
CPU7: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 7: Syncing TSC to CPU 0.
CPU 7: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 936 cycles)
SMP alternatives: switching to SMP code
Booting processor 8/16 APIC 0x1
Initializing CPU#8
Calibrating delay using timer specific routine.. 4800.02 BogoMIPS (lpj=2400010)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 8/1 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
CPU8: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 8: Syncing TSC to CPU 0.
CPU 8: synchronized TSC with CPU 0 (last diff -2 cycles, maxerr 120 cycles)
SMP alternatives: switching to SMP code
Booting processor 9/16 APIC 0x21
Initializing CPU#9
Calibrating delay using timer specific routine.. 4799.93 BogoMIPS (lpj=2399968)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 9/21 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 0
CPU9: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 9: Syncing TSC to CPU 0.
CPU 9: synchronized TSC with CPU 0 (last diff -8 cycles, maxerr 960 cycles)
SMP alternatives: switching to SMP code
Booting processor 10/16 APIC 0x3
Initializing CPU#10
Calibrating delay using timer specific routine.. 4799.95 BogoMIPS (lpj=2399975)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 10/3 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
CPU10: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 10: Syncing TSC to CPU 0.
CPU 10: synchronized TSC with CPU 0 (last diff 2 cycles, maxerr 476 cycles)
SMP alternatives: switching to SMP code
Booting processor 11/16 APIC 0x23
Initializing CPU#11
Calibrating delay using timer specific routine.. 4799.94 BogoMIPS (lpj=2399970)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 11/23 -> Node 1
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 1
CPU11: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 11: Syncing TSC to CPU 0.
CPU 11: synchronized TSC with CPU 0 (last diff -6 cycles, maxerr 940 cycles)
SMP alternatives: switching to SMP code
Booting processor 12/16 APIC 0x13
Initializing CPU#12
Calibrating delay using timer specific routine.. 4799.93 BogoMIPS (lpj=2399968)
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 256K
CPU: L3 cache: 12288K
CPU 12/13 -> Node 0
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 9
CPU12: Thermal monitoring enabled (TM1)
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz stepping 02
CPU 12: Syncing TSC to CPU 0.
CPU 12: synchronized TSC with CPU 0 (last diff 0 cycles, maxerr 480 cycles)
SMP alternatives: switching to SMP code
Booting processor 13/16 APIC 0x33
Initializing CPU#13
我给你看看啊， 还有，你发的其他几个相同内容的帖子我删掉了 。 望理解
