LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dec IS
PORT (clk, reset, din: IN BIT;
Vdout, dout: OUT BIT);
END dec;
ARCHITECTURE deca OF dec IS
SIGNAL pe,cef,cefa,vdout1,din_reset:BIT;
--pe –parallel enable sr->sc;并行
--er –correct error,纠错
--vdout-valid data out –remenber data register
SIGNAL ff1,ff3,err,err1,err2,errcheck,ce,neq:BIT;
SIGNAL syn1,syn3:BIT_VECTOR(0 TO 3);
--syndroms 综合计算
SIGNAL ch1,ch3:BIT_VECTOR(0 TO 3);
--Chein output 检错
SIGNAL ch1_or:BIT_VECTOR(0 TO 3);
COMPONENT dep -- dout<=(syn^3!=syn3)
PORT(syn1,syn3:IN BIT_VECTOR(0 TO 3);
dout:OUT BIT);
END COMPONENT;
COMPONENT ffce
PORT(clk,ce,din:IN BIT;
dout:OUT BIT);
END COMPONENT;
COMPONENT decount
PORT(clk,reset:IN BIT;cef,pe,vdout:OUT BIT);
END COMPONENT;
COMPONENT dbuf
PORT(clk,err,vdout,din:IN BIT;
dout:OUT BIT);
END COMPONENT;
COMPONENT dsyn1
PORT(clk,pe,din:IN BIT;
dout1:OUT BIT_VECTOR(0 TO 3));
END COMPONENT;
COMPONENT dsyn3
PORT(clk,pe,din:IN BIT;
dout3:OUT BIT_VECTOR(0 TO 3));
END COMPONENT;
COMPONENT dch1
PORT(clk,err,errcheck,pe:IN BIT;
din:IN BIT_VECTOR(0 TO 3);
dout:OUT BIT_VECTOR(O TO 3));
END COMPONENT;
COMPONENT dch3
PORT(clk,err,errcheck,pe:IN BIT;
din:IN BIT_VECTOR(0 TO 3);
dout:OUT BIT_VECTOR(O TO 3));
END COMPONENT;
BEGIN
c1:dcount
PORT MAP(clk,reset,cef,pe,vdout,vdout1);
b1:dbuf
PORT MAP(clk,err,vdout1,din_reset,dout);
e1:dep
PORT MAP(ch1,ch3,neq);
f1:ffce
PORT MAP(clk,cefa,ch1_or(3),ff1);
f2:ffce
PORT MAP(clk,cefa,neq,ff3);
s1:dsyn1
PORT MAP(clk,pe,din_reset,syn1);
s3:dsyn3
PORT MAP(clk,pe,din_reset,syn3);
h1:dch1
PORT MAP(clk,err,errcheck,pe,syn1,ch1);
h3:dch3
PORT MAP(clk,err,errcheck,pe,syn3,ch3);
din_reset<=din AND NOT reset;
-- ch1_or eq_or gates
ch1_or(0)<=ch1(0);
gen:
FOR I IN 1 TO 3 GENERATE
ch1_or(i)<=ch1_or(i-1)OR ch1(i);
END GENARATE;
--cefa – clock enable p1,p3 – cepa=1 if start of a new word or err
--cefa<=cef OR err;
--err1<= NOT ff3 AND NOT neq AND ff1 AND NOT ch1_or(3);
--err2<= ff1 AND ch1_or(3) AND ff3 AND NOT neq;
--err<=err1 OR err2;
--errcheck<= NOT cef;
END deca;