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Sony’s PS Vita Uses Chip-on-Chip SiP – 3D, but not 3D
At the tail end of last year Sony released their PlayStation Vita, and it was duly torn down by iFixit and others. In due course we took it apart too, though we didn’t post it on our teardown blog.
Sony CXD5315GG in the PlaySation Vita
Inside we found the usual set of wireless chips, motion sensors, and memory, but the key to the increased performance of the PS Vita is the Sony CXD5315GG processor, a quad- core ARM Cortex-A9 device with an embedded Imagination SGX543MP4+ quad-core GPU.
Above I said that we found memory, but actually the only discrete memory that we found on the motherboard was 4 GB of Toshiba flash; and Sony’s specification states that there is 512 MB (4 Gb) regular RAM, plus 128 MB (1 Gb) VRAM (video RAM). In a phone that would tell me that there is memory in a package-on-package (PoP) configuration, mobile SDRAM in the top part and the processor in the bottom part.
However, when we took the part off the board and did a set of x-rays, the side view proved me wrong – it’s a stack, and the close-up shows that there appear to be five dies in there, a thick die at the base, a thinner one immediately on top and three smaller die on top of that. The second die down could be a spacer, since there don’t seem to bond wires going to it.

Side x-ray images of Sony CXD5315GG This immediately led us to speculate – if the second die up is the VRAM, is it wide I/O DRAM, and is it using through-silicon vias (TSVs)? Time for a real cross-section to check that out, and almost predictably we were disappointed:

Sony CXD5315GG package cross-sectioned
This type of face-to-face connection showed up back in 2006 in the original Sony PSP, and Toshiba had dubbed it “semi-embedded DRAM”, now they are calling it “Stacked Chip SoC”. The ball pitch is an impressive ~45 µm, almost as tight as TI’s copper pillars, but they are staggered to achieve 40-µm pitch.
So what are the five chips that are in the stack? At the base we have the processor chip; face to face with it is a Samsung 1-Gb wide I/O SDRAM; and the top three dies comprise two Samsung 2-Gb mobile DDR2 SDRAMs, separated by a spacer die, and conventionally wire-bonded. The base die is ~250 µm thick, and the others ~100 – 120 µm.
When we look at the die photos of the processor and the 1-Gb memory, we can see that they are purposely laid out for the stacked-chip configuration, since in the centres of both is an array of matching bond pads.



你能翻译下咩

文章转自chipworks
原文自己勉强能看懂。就不在这里翻译现眼了。。

等于白发了

跪求翻译帝～鸟语无力～

无机酸路过

看了一点。
大体上就是说PSV的CPU内存架构没有他宣传的那么好。用的还是PSP的架构。

看完了，大概就是说的像老式CPU一样整合不好，如同和 APU IVB的区别。

说这么多想表达什么，证明他是硬件帝？？？在结论帝面前都是浮云

和PSP架构相同的话，就不难解释PSV直接向下兼容PSP游戏了